
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
26
Maxim Integrated
DIN
SCLK
DOUT
tCSW
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
CS
DEVICE 0
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
DEVICE 6
DEVICE 7
Figure 14. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices
To ensure that all devices have their data ready, con-
nect DRDYIN of device 0 to ground, and connect
DRDYIN of device n to the DRDYOUT of device n-1 for
all devices. DRDYOUT does not go low until DRDIN is
low and the conversion of the device is complete. In this
configuration, DRDYOUT of the last device goes low only
when all devices in the chain have their data ready.